Theseus Logic, Inc.

1080 Montreal Ave, Suite 200
St. Paul, MN 55116
12 Employees

SBIR Award Summary

Total Number of Awards 5
Total Value of Awards $1.93MM
First Award Date 06/12/97
Most Recent Award Date 09/24/99

Key Personnel

Last Name Name Awards Contact
Ferguson Dennis Ferguson 1
Fant Karl Fant 3
Jorgenson Ryan Jorgenson 1
Smith Ross Smith 1

5 Awards Won

Phase 2 SBIR

Agency: Army
Topic: A98-136
Budget: 09/24/99 - 09/30/01

It is clear that continuing to seek performance improvement using traditional digital design and implementation techniques will not provide the "next order of magnitude" improvement in DSP performance. Theseus Logic is commercializing a unique technology that will facilitate low power, system level IC design. NULL Convention Logic - is a new a...

Phase 1 SBIR

Agency: Army
Topic: A98-136
Budget: 12/18/98 - 06/18/99

Theseus Logic has developed and demonstrated a proprietary new logic family, NULL Convention Logical (NCL), which integrates data transformation and control into a single expression thus producing inherently clockless, data driven, and effectively delay insensitive circuits and systems. Theseus proposes to take advantage of the NCL circuits dev...

Phase 1 STTR

Institution: SUNY Stony Brook

Agency: Missile Defense Agency
Topic: BMDO98T002
Budget: 08/15/98 - 02/15/99

The Theseus Logic/SUNY-Stony Brook team is proposing to develop, demonstrate and commercialize Rapid Single Flux Quantum (RSFQ) circuit designed using NULL Convention Logic (NCL). Phase I of this program will demonstrate, by simulation and modeling, the feasibility of implementing logic gate structures in RSFQ technology which can exploi the eff...

Phase 2 SBIR

Agency: Missile Defense Agency
Topic: BMDO97-010
Budget: 02/02/98 - 02/02/00
PI: Karl Fant

The Cascade processor is a revolutionary architecture for digital processors which offers performance benefits unattainable by any other means. It provides a complete and general solution to delay insensitive, event driven, generally concurrent and adaptive processing. The Cascade Processor is a direct result of NULL Convention Logic - a symbo...

Phase 1 SBIR

Agency: Missile Defense Agency
Topic: BMDO97-010
Budget: 06/12/97 - 12/31/97
PI: Karl Fant