Stream Processors, Inc.

455 Deguigne Dr
Sunnyvale, CA 94085
http://www.streamprocessors.com
83 Employees

SBIR Award Summary

Total Number of Awards 5
Total Value of Awards $1.77MM
First Award Date 07/01/04
Most Recent Award Date 09/15/09

Key Personnel

Last Name Name Awards Contact
Khailany Dr. Brucek Khailany 4
Rao Dr. Raghunath Rao 1 Message
Dally Dr. William J. Dally 1 Message

5 Awards Won

Phase 2 SBIR

Agency: Defense Advanced Research Projects Agency
Topic: SB072-008
Budget: 09/15/09 - 03/15/11

Stream processors form a new class of architectures that offers performance scalable to TeraOPS on a single chip, have cost and power efficiency comparable to ASICs, and are completely software programmable from high-level languages. Stream processor technology was developed over 8 years from 1997-2004 of DARPA-funded research on the Imagine pro...

Phase 1 SBIR

Agency: Defense Advanced Research Projects Agency
Topic: SB072-008
Budget: 03/18/08 - 11/06/08

Stream processors form a new class of architectures that offers performance scalable to TeraOPS on a single chip, have cost and power efficiency comparable to ASICs, and are completely software programmable from high-level languages. Stream processor technology was developed over 8 years from 1997-2004 of DARPA-funded research at Stanford Univer...

Phase 2 SBIR

Agency: Army
Topic: A04-025
Budget: 01/20/06 - 01/20/08

Stream Processors (SPs) form a new class of image processors that offer performance scalable to Teraops, have efficiency comparable to ASICs, and are completely programmable from high-level languages. SP technology was developed over 8 years of DARPA-funded research in Stanford University that resulted in a working prototype IC, 3rd-generation s...

Phase 1 SBIR

Agency: Army
Topic: A04-025
Budget: 02/10/05 - 08/10/05

Stream processors can provide 100s of GOPS of performance at low power levels with full programmability from high-level programming languages. SPI proposes to evaluate the applicability of these stream processors to remote surveillance systems where tens to hundreds of GOPS of performance and interfacing to a variety of sensors is required. As...

Phase 1 STTR

Institution: University of Colorado - Colorado Springs

Agency: Navy
Topic: N04-T028
Budget: 07/01/04 - 04/30/05

Intelligent imaging systems of the future require Teraops of arithmetic performance with low power dissipation. However, they also demand full programmability and functionality over a wide range of application characteristics present in intelligent imaging systems. Stream processors have recently emerged as a technology that can provide Teraops...