CPU Technology, Inc.

5731 W. Las Positas Boulevard
Pleasanton, CA 94588
http://www.cputech.com
55 Employees

SBIR Award Summary

Total Number of Awards 10
Total Value of Awards $6.89MM
First Award Date 08/31/93
Most Recent Award Date 09/24/08

Key Personnel

Last Name Name Awards Contact
Lincoln Mr. Daniel J. Lincoln 1 Message
Swensen Dr. John Swensen 1 Message
Walters Gail Walters 5
Dyer Mr. Brad Dyer 1 Message
Smith Scott Smith 1
Scheitrum Mr. Mark Scheitrum 1 Message
Tracy Mr. Tom Tracy 1
Young Mr. Bill Young 1 Message

10 Awards Won

Phase 2 STTR

Institution: University of Maryland

Agency: Navy
Topic: N06-T005
Budget: 09/24/08 - 03/24/10

The objective is to investigate further the advantages of applying 4th generation deeply-coupled computing architectures and adaptive processing techniques to STAP. Specifically, we will explore building a STAP radar processor using this technology that has the appropriate format factor, throughput and capability to perform real-time, full degr...

Phase 1 STTR

Institution: University of Maryland

Agency: Navy
Topic: N06-T005
Budget: 08/01/06 - 05/31/07

Warfare is changing; there is a need for airborne and space-based sensor systems to detect small, highly maneuverable targets against a strong clutter background in the presence of jamming. Space-Time Adaptive Processing (STAP) is a new signal processing technique for advanced radar systems that allows for performance enhancements over conventi...

Phase 1 SBIR

Agency: Air Force
Topic: AF05-225
Budget: 03/18/05 - 12/18/05

CPU Tech will develop algorithms for efficient signal processing for Receiver-on-a-Chip. The marriage of these technologies is possible in the desirable form factor through deep sub-micron development. The application at hand demands signal processing algorithms and system level development tools in addition to this technology. This approach,...

Phase 2 SBIR

Agency: Navy
Topic: N03-031
Budget: 01/18/05 - 01/18/07

The objective of this proposal is to develop a preliminary brassboard implementation for an H-60 system and for the AN/ALE-47, and demonstrate the interfaces through simulated flight using the ADVAYK brassboard. All designs will be virtually simulated and validated to ensure the desired behavior of the existing system is captured. The designs...

Phase 1 SBIR

Agency: Navy
Topic: N03-031
Budget: 07/28/03 - 01/28/04

This proposed effort is an analytical assessment of the applicability of compatible system-on-chip modernization and technology insertion into H-60 Mission Avionics. The principal issue is to determine the extent of SOC integration within H-60 avionics that is possible in an affordable and timely manner. CPU Tech has developed and put into pract...

Phase 2 SBIR

Agency: Air Force
Topic: AF93-158
Budget: 04/29/03 - 04/29/05

The objective is to design a modern very high performance microprocessor that will 1) execute existing MIL-STD-1750A software at the binary level, without modification or recomplilation, 2) solve the memory addressing and performance limitations of the 1750A, and 3) permit new avionics software to be developed that will utilize the characteristi...

Phase 2 SBIR

Agency: Air Force
Topic: AF98-060
Budget: 12/09/99 - 12/09/01

The requirement for readily available rad-hard digital processing components is an increasingly serious concern. Government and commercial users of radiation-hardened electronics want to leverage available commercial-off-the-shelf (COTS) electronics, specifically in the area of software development environments and tools. However, an affordable,...

Phase 1 SBIR

Agency: Air Force
Topic: AF98-060
Budget: 04/30/98 - 04/10/99

Phase I is an experiment to demonstrate the feasibility of a radiation/hardened Processor Development Methodolgy (RH-PDM) for translating commercial processor designs to radiation-hardened (rad-hard) doundry libraries. The proposed methodology is very low-risk, repeatable, and foundry process independent. The work effort for this experiment co...

Phase 2 SBIR

Agency: Air Force
Topic: AF93-158
Budget: 09/29/94 - 03/29/96

The objective is to design a modern very high performance microprocessor that will 1) execute existing MIL-STD-1750A software at the binary level, without modification or recomplilation, 2) solve the memory addressing and performance limitations of the 1750A, and 3) permit new avionics software to be developed that will utilize the characteristi...

Phase 1 SBIR

Agency: Air Force
Topic: AF93-158
Budget: 08/31/93 - 02/06/94

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