Tezzaron Semiconductor Corp.

1415 Bond Street Array
Naperville, IL 60563
http://www.tezzaron.com
165 Employees

SBIR Award Summary

Total Number of Awards 12
Total Value of Awards $5.61MM
Active Awards 1 valued at $1000K
First Award Date 01/15/08
Most Recent Award Date 08/01/16

Key Personnel

Last Name Name Awards Contact
Patti Mr. Robert Patti 13 Message
Patti Robert Patti 2 Message

12 Awards Won

Phase 2 SBIR Active

Agency: Department of Energy
Topic: 30f
Budget: 08/01/16 - 07/31/18

Siliconbased detectors are central to all modern particle physics collider experiments. The functional area of these systems has increased from a few square centimeters in the mid80s to 200 square meters for the CMS tracker in the early 2000s. Upgrades being considered for the high luminosity LHC will require more than 200 square meters for CMS ...

Phase 2 SBIR

Agency: Air Force
Topic: AF141-250
Budget: 06/22/15 - 09/21/17

ABSTRACT:In Phase II Tezzaron will design a 2 layer 8Mb ReRAM (RRAM) memory device, extendable to 17 layers or 128Gb as a test chip or 1Gb as a final device. The first layer of the design is a controller layer with power control, drivers, user interface circuitry (i.e. peripheral circuitry), and sense amplifiers. The second layer of the design h...

Phase 1 SBIR

Agency: Department of Energy
Topic: 30f
Budget: 06/08/15 - 03/07/16

Silicon-based detectors are central to all modern particle physics collider experiments. The functional area of these systems has increased from a few square centimeters in the mid-80s to 200 square meters for the CMS tracker in the early 2000s. Upgrades being considered for the high luminosity LHC will require more than 200 square meters for CM...

Phase 1 SBIR

Agency: Air Force
Topic: AF141-250
Budget: 09/23/14 - 03/30/15

ABSTRACT: ReRAM has made significant progress over the last few years and is ready for development by early adopters. Tezzaron proposes to create a multilayer 3D assembled ReRAM memory device using Rambus ReRAM technology and Honeywell RH wafers. The phase II target device will be radiation hardened, low power, non-volatile and have a density i...

Phase 1 SBIR

Agency: Air Force
Topic: AF141-097
Budget: 06/20/14 - 03/02/15

ABSTRACT: Tezzaron proposes to create a microprocessor device based on an ARM M0 processor designed to be fabricated in the Honeywell S150 Rad-Hard SOI semiconductor process. The device will be designed for both stand alone and 3D circuit integration. In a 3D application the device can be die to wafer or wafer to wafer assembled providing a core...

Phase 2 SBIR

Agency: Air Force
Topic: AF103-093
Budget: 08/15/12 - 11/15/14

ABSTRACT: Tezzaron proposes to develop and demonstrate a 64Mb 3D integrated MRAM device comprising one non-volatile memory cell layer and one radiation hardened I/O logic and control layer. This memory device will address the industry s next generation needs for nonvolatile memory density and also, because of its virtually unlimited wearout life...

Phase 1 SBIR

Agency: Air Force
Topic: AF103-093
Budget: 02/18/11 - 02/18/12

ABSTRACT: Tezzaron intends to develop a nonvolatile low latency memory based on 3D assembly of RRAM memory cell wafers with CMOS logic wafers. The very high density 3D interconnect that Tezzaron can produce allows circuitry to be manufactured on different wafers in different semiconductor processes and then integrated into a single polylithic su...

Phase 1 SBIR

Agency: Defense Advanced Research Projects Agency
Topic: SB091-008
Budget: 12/29/09 - 08/30/10

Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyond the capability of current commercial technology. A device of this density can offer significant improvements in system power, size, weight and p...

Phase 2 SBIR

Agency: Air Force
Topic: AF073-099
Budget: 08/26/09 - 10/31/11

Two radiation hardened 3D integrated circuit memory devices will be fabricated under this effort. The 3D devices are created by the wafer level 3D bonding of separate silicon substrates. Within each of the ~200 die in the resultant wafer stack, there some 5 million vertical interconnects. The very high level of 3D interconnect allows unprecedent...

Phase 1 SBIR

Agency: Air Force
Topic: AF083-208
Budget: 02/13/09 - 01/13/10

Tezzaron proposes to use its 3D wafer stacking technology to produce a true 3 dimensional fabric of programmable logic. A benefit of 3D integration is the fundamental increase in interconnect. FPGAs by their nature use huge amounts of interconnect and in normal 2D implementations, they often have an industry leading number of metal layers used. ...

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