Scalable, High-speed Nonvolatile Memory-based Hardware Encryption

Period of Performance: 07/10/2003 - 01/09/2004


Phase 1 SBIR

Recipient Firm

Celis Semiconductor Corp.
5475 Mark Dabling Blvd., Suite
Colorado Springs, CO 80918
Principal Investigator


An encryption chip design is envisioned that utilizes medium to large capacity nonvolatile memory to achieve ultra high-speed encryption as opposed to common implementations of high-speed encryption algorithms that are processor-based. The design will address the security issue that comes with the increased data exposure of high-speed encryption where the probability of breaking the code through cryptanalysis increases with the amount of sampled ciphertext data. The design will ideally be immune to reverse engineering, active tampering and eavesdropping. It will feature scalable security as a function of the memory size and scalable speed as a function of memory bus width. This scalability enables a methodology whereby a particular configuration can be adjusted to balance the cost-benefit in the target application. The design will provide benefits for highly secure, high-speed encryption applications where upgrading the encryption capability at regular intervals is a requirement. The following application areas should benefit: 1. Military communications, both terrestrial and space, 2. Internet backbone physical layer transmissions, and 3. Wireless network physical layer transmissions.