A low power, high-speed, radiation hard analog to digital converter (ADC) using FLEXFET technology

Period of Performance: 07/22/2003 - 01/21/2004


Phase 1 SBIR

Recipient Firm

Ridgetop Group, Inc.
3580 West Ina Road Array
Tucson, AZ 85741
Principal Investigator


The best currently available fast Analog to Digital Converters cannot achieve power consumption below 300 mW/Ms/bit. Ridgetop proposes to design a pipeline architecture ADC that will break this barrier using the revolutionary 0.25 mm FLEXFET device. Because this device is built on Silicon On Insulator (SOI) material, and the oxides have been hardened, it is radiation hard for total dose, single event upset and dose rate (prompt) events The FLEXFET SOI RF-CMOS device is essentially equivalent to a fully self-aligned double-gated MOSFET, which is widely accepted as the next device on the ITRS CMOS roadmap. The FLEXFET is flexible, in that it provides four different unique configurations appropriate to various circuit applications, all with rad-hard, low-power, high frequency operation. The battery or power supply comprises a large percentage of the cost, size, weight, and reliability problems in current RF devices. As these systems become more highly integrated by utilizing scaled RF-CMOS devices, the power dissipation will become an even greater concern. Pipelined ADC's are found in CCD cameras, ultrasonic imaging, digital receiver, digital video and communications equipment. Clearly, reducing the amount of power required would greatly benefit these applications by reducing the battery weight or extending battery life. The MDA mission would be similarly impacted