Optical clock distribution in 65nm CMOS process node

Period of Performance: 06/15/2011 - 03/14/2012


Phase 1 STTR

Recipient Firm

APIC Corporation
5800 Uplander Way
Culver City, CA 90230
Principal Investigator
Firm POC

Research Institution

Massachusetts Institute of Technology
77 Massachusetts ave
Cambridge, MA 02139
Institution POC


ABSTRACT: Electrical interconnects implemented with metal wires inside computer chips or between computer chips are becoming the critical performance bottle neck due to limited bandwidth, increased power dissipation and crowded input/output interfaces. Using optics for interconnects solves the bandwidth problem, reduces the overall power dissipation by eliminating charging of interconnect lines and can combine on the same waveguide multiple wavelengths to allow single output to carry parallels bytes of data streams. We propose a process that integrates Ge epitaxy and formation of detectors with advanced CMOS process flow after polysilicon and prior to the full gate formation. This integration sequence ensures that the high temperature Ge growth steps do not perturb the gate channel and alter the CMOS performance. Special steps for protection of the Ge from CMOS high temperature activation steps are proposed. Additional re crystallization step will be tested. An optical waveguide suspended over the silicon and implemented in the ILD is described and will be fabricated. An optimized optical interconnect link will be designed with the requirement to be fully compatible with 65nm CMOS process. BENEFIT: High performance computer chips, avionics networks, telecommunications