Integrated High-Complexity Systems in Silicon Photonics

Period of Performance: 07/01/2011 - 12/31/2011


Phase 1 STTR

Recipient Firm

Portage Bay Photonics
214 Summit Avenue E, #402
Seattle, WA 98102
Principal Investigator
Firm POC

Research Institution

University of Washington
Department of Aeronautics&Astronautics, Box 352250
Seattle, WA 98195
Institution POC


ABSTRACT: We propose to develop and validate (in phase I) detailed designs for highly scaled silicon photonic-electronic chips for applications relevant to the DOD in high-bandwidth data communication. This effort will be closely coordinated with the OPSIS (Optoelectronic Systems Integration in Silicon) project being led at the University of Washington, an effort to create an open foundry process for silicon photonic-electronic integrated circuits and to develop a comprehensive design kit for electronic-photonic integrated circuits (EPICs) in silicon. While that effort is aimed at developing design rules and device libraries in a bottom-up approach, the effort proposed here is a top-down approach, driven by system-level needs for high-speed data links both on-chip and chip-to-chip. We will work to take the models created and extracted based on the OPSIS chips, and use them to model systems where highly-scaled EPIC circuits will provide key advantages for military systems. In particular, we will make use of the recently released software and simulation tools developed in the Bergman Laboratory at Columbia (PhoenixSim - ( in order to develop a comprehensive system modeling framework for the OPSIS EPIC chips, and we will use this framework to model two different types of systems, each of which we expect to benefit significantly from highly scaled optoelectronic integration. The two test systems we intend to investigate in phase I are: (1) A high-bandwidth data communication system aimed at short-reach (