Radiation-Hardened, Resistive Random Access Memory

Period of Performance: 02/18/2011 - 02/18/2012

$100K

Phase 1 SBIR

Recipient Firm

Tezzaron Semiconductor Corp.
1415 Bond Street Array
Naperville, IL 60563
Principal Investigator

Abstract

ABSTRACT: Tezzaron intends to develop a nonvolatile low latency memory based on 3D assembly of RRAM memory cell wafers with CMOS logic wafers. The very high density 3D interconnect that Tezzaron can produce allows circuitry to be manufactured on different wafers in different semiconductor processes and then integrated into a single polylithic substrate that acts as if were a single circuit. The combination of traditional CMOS and RRAM technology in a 3D integrated circuit allows exploitation of a new higher risk technology such as RRAM but with the confidence of using well known circuit design techniques and existing processes for much of the new component. The 3D integrated circuit approach also addresses another critical concern which is yield. Newer process technologies are plagued by low yields stemming from inferior material purity. This is a know issue with many experimental materials employed in RRAMs. 3D integration permits enhanced repair and redundancy due to the use of the high speed CMOS logic process and the additional wiring capacity 3D integration affords. This is a requirement for commercialization of large high density memories fabricated with any of the possible RRAM technologies. BENEFIT: It is anticipated the final device will provide a high density nonvolatile memory with high radiation tolerance. The development of a low latency random access nonvolatile memory developed with 3D integration addresses the commercial issues that are limiting acceptance RRAM technology. The technology will have direct use in many commercial and consumer devices, especially handheld devices such as smart phones and PDAs.