Self-Assembly Production of Hybrid CMOS/Nanodevice Interconnects

Period of Performance: 09/10/2008 - 09/10/2010

$730K

Phase 2 SBIR

Recipient Firm

Nanosonic, Inc.
158 Wheatland Drive Array
Pembroke, VA 24136
Principal Investigator

Abstract

The objective of this Army Phase II SBIR program is to transition demonstrated wet chemistry molecular electronic device manufacturing concepts to both near-term defense system applications, and the longer-term development of a broader range of electronic and optoelectronic device functionalities. The Phase I SBIR program demonstrated the feasibility of fabricating high performance thin film transistors (TFTs), nonvolatile bi-stable MOSFET memory devices, and initial 2x2 memory arrays, using a combination of surface functionalized nanocluster chemistry, molecular level self-assembly, and sub-micron spatial device patterning. Materials analysis and macro-level device I/V characteristics proved that design and control of nanocluster surface functionalization chemistry can be translated into practical electronic device performance. During the Phase II program, NanoSonic would extend and improve molecular electronic chemistry designs, optimize the charge transport and effective bandgap properties of semiconductor nanoclusters and nanotubes, improve electrostatic self-assembly processing and in-plane patterning manufacturing methods, and produce operational prototype devices. These devices would be incorporated into multiple near-term military system demonstrators with a major U.S. defense prime contractor for ground, ship and air applications. Device fabrication would include the incorporation of functional nanocluster and nanotube materials synthesized in-house and obtained from U.S. research groups and companies, and comparative analysis of resulting performance.