Dynamic Hardware Development Methodology for FPGAs

Period of Performance: 06/23/2008 - 08/24/2010

$750K

Phase 2 SBIR

Recipient Firm

Luna Innovations, Inc.
301 1st St Suite 200
Roanoke, VA 24011
Principal Investigator

Abstract

Configurable computing devices, such as Field Programmable Gates Arrays (FPGAs), permit arbitrary reprogramming of the devices hardware structure after manufacture. This programmability greatly decreases development costs and time-to-market compared to Application-Specific Integrated Circuits (ASICs). Almost all commercial designs using FPGAs treat the configurable logic as static in the deployed product. Previous research on Run-Time Reconfiguration (RTR) has demonstrated performance benefits from partially or fully reconfiguring an FPGA during operation. Unfortunately, developing RTR applications has been a difficult undertaking. FPGA design tools share a lineage with ASIC tools, with both assuming static hardware. What little vendor support that has been available forced the designer to do much of the low-level implementation manually. Commercial tools in the form of design capture methodologies and simulators are non-existent. The objective of this project is to define an architecture-agnostic RTR application development methodology, incorporating the latest advances and trends in configurable computing. Addressing the deficiencies in previous research, the proposed research enables the use of commercial design entry and simulation tools, fully incorporates embedded processors into the computational and programming models, and permits partial reconfiguration of one or more FPGAs through automatic generation of custom configuration controllers.