Coherent Distributed Aperture Enabled Active Electronically Steered Array (CDA-AESA)

Period of Performance: 11/01/2007 - 04/30/2008

$100K

Phase 1 STTR

Recipient Firm

Applied Radar, Inc.
315 Commerce Park Road, Unit 3
North Kingstown, RI 02852
Principal Investigator
Firm POC

Research Institution

Massachusetts Institute of Technology
77 Massachusetts ave
Cambridge, MA 02139
Institution POC

Abstract

Our missile defense capability crucially depends on radar performance to detect, track and discriminate hostile targets. New radar designs being developed offer enhanced capability. However, a significant impediment to the deployment of these new radars is the high cost of active electronically scanned arrays (AESAs) and in particular the antennas upon which they are based. Together with our internationally recognized research partner, we propose a design-to-cost research effort to demonstrate reduced cost AESAs that enable highly capable coherent distributed aperture (CDA) radar systems. This work will leverage previous investments by Applied Radar, Inc. in AESA technology, providing proof-of-concept hardware and a possible alternate low-cost SPEAR array solution meeting the system requirements. The hardware consists of a wideband array, T/R module, digital receiver/exciter (DREX) and digital beamformer (DBF). The new array hardware is capable of supporting a 4X increase in system bandwidth over the current capability. Degrees of freedom (DOF) reduction techniques are used at the array aperture level in order to reduce the digital data flow and simplify the design without compromising performance. An open systems architecture is utilized throughout the hardware development to allow incremental improvements to various components of the system. The AESA array demonstrator is designed to fit within a scalable architecture and can be sized to meet the needs of various applications. In Phase I, a conceptual design to meet SPEAR requirements will be designed around existing Applied Radar hardware, utilizing CDA concepts. In Phase II a hardware demonstrator will be built and tested.