Novel Architectures Development

Period of Performance: 01/15/2008 - 09/12/2008


Phase 1 SBIR

Recipient Firm

Mymic LLC
Portsmouth, VA 23703
Principal Investigator


Available parallelism in a computer program, whether Instruction Level Parallelism (ILP) or Task Level Parallelism (TLP), offers the opportunity for improved performance by identifying independent instructions to execute concurrently. At the architectural level, superscalar and Very Large Instruction Word (VLIW) architectures address ILP while multithreaded architectures address TLP. Superscalar and VLIW architectures require no changes in programming paradigms, but multithreaded architectures require threaded applications. It is proposed that by looking at specific problem domains, TLP can be found through enhanced hardware support without changing the programming paradigm. The Discrete-Event Simulation Central Processor Unit (DESCPU) proposed here addresses inherent TLP in discrete-event simulations (DES). DES involves the execution of events at scheduled simulation times, with the potential for concurrent events at the same simulation time. This inherent property of the paradigm opens the opportunity for Event-Level Parallelism (ELP) as a subset of TLP. DESCPU would provide an enhanced Instruction Set Architecture (ISA) acting as an interface between the simulation executive and the hardware for event scheduling and execution. DESCPU would also provide hardware support for maintaining event lists and invoking events for execution. DESCPU would also provide multiple event execution paths to support concurrent event execution, while sharing common functional units.