Sensor Processing and Image Fusion for Passive Target Recognition on a Reconfigurable Processor

Period of Performance: 06/10/1998 - 12/10/1998


Phase 1 STTR

Recipient Firm

Information Systems Laboratories, Inc.
10070 Barnes Canyon Road Array
San Diego, CA 92121
Principal Investigator
Firm POC

Research Institution

University of California, San Diego
9500 Gilman Drive, #0411
La Jolla, CA 92093
Institution POC

Research Topics


The demand for carrying out a complete signal processing task, from multiple sensor output processing to feature extraction to automatic target identification and recognition on a physically restricted platform such as a UAV demands that the signal processor hardware perform all the tasks with minimal hardware. Thus, the hardware must be reconfigurable. The recent advances in the processing power of FPGA's makes such a signal processor attainable. ISL proposes to use its extensive experience in Reconfigurable hardware development and Pattern Recognition to develop an multi passive-imaging system for ATR on a UAV platform. This system will fuse output from multiple imaging devices (CCD arrays, infrared imagers, and millimeter wave imagers) using a novel image combining algorithm with a rule base to fuse the images, use universal classification to prescreen the data, and use a Gram-Schmidt method or a neural network to classify the data. The rapid pace of development in FPGA technology will allow all these functions to be performed on a reconfigurable processor architecture.