Confinement of Threading Dislocations at the CdTe/Si Interface for Improved HgCdTe IR Sensors

Period of Performance: 08/01/2006 - 01/28/2007


Phase 1 STTR

Recipient Firm

Wizdom Systems, Inc.
1300 Iroquois Avenue, Suite 140
Naperville, IL 60563
Principal Investigator
Firm POC

Research Institution

University of Illinois, Chicago
809 S Marshfield RM 608
Chicago, IL 60612
Institution POC


Stringent requirements on the performance of third generation HgCdTe infrared detectors demand the availability of affordable high quality substrates with very large areas. The large areas are needed both for the fabrication of single very large focal plane arrays (FPAs) (2048x2048) and to increase the yield of smaller size FBAs per wafer. The quality of commercial CdTe/Si technology, the best large-area composite substrate available for the epitaxial growth HgCdTe, has reached a plateau such that significant improvements using current growth techniques are doubtful. However, the growth of CdTe on Si/Si (and potentially on Ge/Si) twist-bonded substrates (TBS) promises to transform this technology to markedly higher quality levels. We propose the epitaxial growth of CdTe on Si/Si substrates by Molecular Beam Epitaxy (MBE) as a promising method to prepare CdTe layers. Such layers will have significantly reduced threading dislocation density at the CdTe surface than what is available today. The CdTe/Si substrates will then be used as composite substrates for the growth of large area HgCdTe epilayers. We further propose to identify the requirements and design a high vacuum wafer bonding system for the fabrication of Si/Si and Ge/Si twist bonding structures.