A Partitioner for ULSI Synthesis Engineering (PAUSE)

Period of Performance: 05/05/1999 - 02/05/2000


Phase 1 SBIR

Recipient Firm

Edaptive Computing, Inc.
1245 Lyons Road Array
Dayton, OH 45458
Principal Investigator

Research Topics


EDAptive Computing, Inc. (EDAptive) and Dr. Ranga Vemuri of the University of Cincinnati (UC) present a unique and commercially-viable solution to the problem of implementing ULSI ASIC system functionality using VHDL-level partitioning. Our PArtitioner for ULSI Synthesis Engineering (PAUSE) program will apply innovative genetic partitioning algorithms to solve this problem. Given functional or structural specifications in VHDL at various levels of abstraction (behavioral, RTL, or gate) and multichip constraints (pinout, die speed, multichip packaqe speed, die area, multichip package area, timing constraints including clock speed and throughput), our proposed partitioning tool will generate a partitioned multichip design meeting those constraints in VHDL. In this proposal we present a focused approach to establish feasibility of our partitioning algorithms in Phase I, and to (1) prove the concept through interaction with synthesis tools to partition high-level design in VHDL, and (2) prepare for technology transition in Phase II. The major Phase I results will be (1) A Demonstration of critical design aspects, and (2) A Final Report documenting all the investigations, decisions, findings, commercialization strategy, and demonstrations occurring during the Phase I program.