Integrated Electronics for Vertical (CPP) GMR MRAM

Period of Performance: 04/09/1999 - 10/31/1999


Phase 1 SBIR

Recipient Firm

Nonvolatile Electronics, Inc.
11409 Valley View Road Array
Eden Prairie, MN 55344
Principal Investigator

Research Topics


This SBIR Phase I proposal will demonstrate the feasibility of integrating current-perpendicular-to-the-plane (CPP), or vertical giant magnetoresistance (VGMR), memory cells with VLSI silicon electronics. VGMR memory technology enables ultra-high density storage capability which is predicted to surpass DRAM. Unlike DRAM, however, VGMR MRAM (magnetoresistive random access memory) is nonvolatile, meaning it retains its state even without power. In order to fully exploit the benefits of this emerging technology, it will need to be implemented using high density silicon electronics. In order to demonstrate the feasibility of building the VGMR memory the following four objectives will be met: a) identify vertical memory specifications and constraints; b) identify memory array and integrated circuit process limitations; c) design vertical memory architecture; and d) design vertical memory circuitry. With the close of the Phase I effort, NVE will have completed a preliminary VLSI circuit design, predicted device performance and yield requirements, and outlined a process for fabricating integrated VGMR memory arrays. Under Phase II, VGMR arrays will be tested and debugged using multi-chip integrated prototypes followed by fabrication and demonstration of single chip VGMR arrays fully integrated with silicon-based VLSI electronics.