On-Fpa Aanalog Nonuniformity Correction

Period of Performance: 04/22/1998 - 10/21/1998

$64.7K

Phase 1 SBIR

Recipient Firm

Pacific Advanced Technology
1607 Mission Dr. Suite 301 Array
Solvang, CA 93464
Principal Investigator

Abstract

Occasionally, a technology is developed which revolutionizes systems and permits an enabling advancement in an industry. This proposal describes an advancement which will have a profound impact on systems that the Ballistic Missile Defense Organization will use in the future. Infrared focal plane arrays (FPAs) have historically required the post-processing operations of two-point spatial nonuniformity correction (NUC) to compensate for gain and offset variations between the thousands (or hundreds of thousands) of pixel channels on the device. Through the development of other on-FPA features which have been implemented in the analog domain in massively parallel implementations, Pacific Advanced Technology (PAT) has laid the groundwork for the application of a complete automatic two-point NUC operation which could be hosted directly on the FPA itself. Test structures which have been included on a recent PAT-designed silicon wafer produced with 0.5 micron CMOS technology at the Hewlett Packard MOSIS foundry will be available to this program with no investment of time or money. This program will characterize the performance of the existing CMOS test structures and produce the design for a complete NUC implementation for a highly integrated FPA of at least 256 x 256 pixels in size.