Very High Speed Integrated Circuit Hardware Description Language (VHDL) Models for Backplane Open System

Period of Performance: 05/08/1998 - 02/08/1999


Phase 1 SBIR

Recipient Firm

RAM Laboratories, Inc.
591 Camino de la Reina Suite 610
San Diego, CA 92108
Principal Investigator

Research Topics


Because of the large costs associated with developing state-of-the-art systems, today's military has turned toward developing systems based on backplane open architecture standards. Developing systems based on such standards allows for the inclusion of commercial off-the-shelf components in the development of military systems. However, existing models which promote the top-down design and analysis of such systems are lacking, if not non-existent. The Phase I effort will lay the groundwork for the development of hardware models to support top-down development of backplane open system architectures. This effort will define the types of modeling paradigms, modeling targets, and bus protocols which will be required to support backplane open architecture design at various levels of design detail.