An Optimized Turbo Codec

Period of Performance: 05/13/1998 - 02/13/1999


Phase 1 SBIR

Recipient Firm

Lincom Corp.
5110 West Goldleaf Circle, Suite 250
Los Angeles, CA 90056
Principal Investigator


LinCom proposes the design of a codec (encoder-decoder) VLSI product using the Turbo codes which will overcome the latency and BER floors which have been associated with these codes. We are proposing a new innovative technique which will hopefully provide performance comparable to Turbo codes but without the delay and complexity penalties. The resulting product would provide BER's below 10-9 with modest latency and complexity and high coding gain. The Phase I effort will consist of: a) performing a trade study of possible codes designs; b) select a limited number of candidate designs based on BER performance, data throughput, and latency; and c) select the candidate design which is most suitable for implementation in VLSI hardware. Some of the areas to be investigated include the Turbo Interleaver size and type, the types of CC's and their code rates, serial vs parallel concatenation, puncturing method, and the structure of the interleavers. Also to be investigated will be the complexity of the implementation, the required computational speed, and gate count.