Low Cost Space Hardened Power MOSFET

Period of Performance: 04/30/1998 - 04/10/1999

$100K

Phase 1 SBIR

Recipient Firm

Space Electronics, Inc.
4031 Sorrento Valley Blvd.
San Diego, CA 92121
Principal Investigator

Research Topics

Abstract

This cross-cutting technology provides a truly innovative, cost effective approach to space hardened power MOSFETs based on commerical-off-the-shelf (COTS) technology. The problem to be solved is the development of a simple technique to harden power MOSFETs to Single Event Gate Rupture (SEGR) while not compromisong and perhaps improving their hardness to total ionizing radiation exposure.At the same time, minor structural modifications would be implemented to reduce Single Event Burnout (SEB) susceptibility. All changes are implementable in a commercial power MOSFET process and fabrication facility. This accomplishment would allow the fabrication of power MOSFETs for application in spaceborne electronics at reduced production costs. The availability of this class of power MOSFETs based on minor modifications of COTS technologies, would decrease system costs and at the same time increase system reliability.This innovate concept will demonstrate the feasibility of using a modified gate oxide structure consisting of a silicon oxide/silicon nitride/ silicon oxide sandwich as a simple technique to harden Vertical Double MOSFETs to SEGR while maintaining their hardness to total ionizing radiation exposure.Phase I will thoroughly explore the parameter of the proposed process modification. An optimal silicon oxide/silicon nitride/silicon oxide layered structure as the gate oxide will be designed.