Bandwidth-Efficient, Low Latency, Scalable Turbo Architecture (BELLSTAR)

Period of Performance: 12/18/1998 - 06/18/1999


Phase 1 SBIR

Recipient Firm

Radix Technologies, Inc.
329 N. Bernardo Avenue
Mountain View, CA 94043
Principal Investigator

Research Topics


This Phase I SBIR program will define and architect a Bandwidth-Efficient, Low-Latency, Scalable Turbo Architecture (BELLSTAR) for detailed FPGA design and implementation during a Phase II SBIR development. The design will focus on a flexible, modular architecture that can be used as both a developmental tool and as a stepping stone toward new generations of high density, low-cost turbo encoder/decoder chips with an appropriate mix of capabilities. As a development tool, the BELLSTAR will provide an open architecture for the analysis, test, and demonstration of the very high coding gains achievable at relatively low latencies for the appropriate data rates and modulation types. Follow-on developments will allow the appropriate mixture of open-architecture components to be reduced using MCM, ASIC, and other novel packaging technologies to produce small, high-density, low-cost turbo codecs for both the military and commercial marketplace. BENEFITS: Potential applications of the architecture, techniques, and components developed on this project include: satellite communications, wireless communications, cable modems, Digital Subscriber Line (DSL) modems, voice-band modems, and most digital data communication applications that can tolerate latency in return for high coding gains. The developmental test-bed can be used as laboratory test equipment for new techniques in more advanced turbo-coding products and applications.