Copper Electrochemical Planarization for Three-dimensional Advanced Ic Multichip Module and Interconnect Applications

Period of Performance: 04/10/1998 - 01/10/1998

$99.9K

Phase 1 SBIR

Recipient Firm

Faraday Technology, Inc.
315 Huls Drive Array
Englewood, OH 45315
Principal Investigator

Research Topics

Abstract

The objective of the program is to develop and commercialize an electrochemical copper planarization process for three-dimensional advanced IC applications (multichip modules and interconnects) based on a modulated reverse electrochemical planarization (MREF-ECP) process. The Phase I program will demonstrate the MREF-ECP process using damascene architecture with trenches of 1 to 0.25 microns and aspect ratios of 1:1 to 3:1. These dimensional features are not currently attained using state-of-the art fabrication techniques. Further, the proposed MREF-ECP process will (1) improve through-put due to the elimination of the time consuming electropolishing step, (2) reduce capital investment with less processing sequences, and (3) minimize or eliminate the waste stream volume. The proposed MREF-ECP process is a key enabling technology for three-dimensional IC applications required by the U.S. Air Force to reduce the power, weight, volume, and cost of aircraft microelectronics.