Core Logic and Field Programmable Gate Array-Based

Period of Performance: 05/28/1998 - 11/28/1998

$69.9K

Phase 1 SBIR

Recipient Firm

Visicom Laboratories, Inc.
10052 Mesa Ridge Court
San Diego, CA 92121
Principal Investigator

Research Topics

Abstract

The object of this effort is to employ VisiCom's considerable experience in reconfigurable logic engines, general computer hardware architecture, and software to show feasibility of combining core logic (mask programmable) microprocessor and FPGA devices. In order to optimize speed, VisiCom will need to examine pipelined and paralled processing approaches. FPGA clock rates are generally below those of core logic parts. Care will be required since certain design implementations will actually cause clock rates to decrease. Designs spanning multiple FPGAs may be afflicted with further speed degradation.