Repeatable, Low-Risk Process-Independent Methodology for Translating Commercial Processor Designs to Radiation-Hardened Foundry Libraries

Period of Performance: 04/30/1998 - 04/10/1999


Phase 1 SBIR

Recipient Firm

CPU Technology, Inc.
5731 W. Las Positas Boulevard
Pleasanton, CA 94588
Principal Investigator

Research Topics


Phase I is an experiment to demonstrate the feasibility of a radiation/hardened Processor Development Methodolgy (RH-PDM) for translating commercial processor designs to radiation-hardened (rad-hard) doundry libraries. The proposed methodology is very low-risk, repeatable, and foundry process independent. The work effort for this experiment consists of translating a commercial processor design to a rad-hard library, and then proving that the results of the methodology are manufacturable, and that the rad-hard and commercial processors are functionally identical. Phase I objectives are: 1) Program CPU Technology tools ro accomodate rad-hard libraries, 2) Synthesize a commercial processor, utilizing the methodology, to rad-hard libraries, 3) Verify commercial-to-rad-hard translated design functionality, 4) Prove process-independence of the methodology by demonstrating manufacturability of the rad-hard design in two independent foundries, and 5) Re-synthesize rad-hard design to commercial design language and execute to verify identical functionality. The foundry analysis will be the ultimate determinant of manufacturability. In Phase II, a government selected processor type will be taken through the entire Processor Development Methodology, beginning with Instruction Set Architecture development.