Secure Processors

Period of Performance: 06/26/2006 - 06/26/2007


Phase 1 SBIR

Recipient Firm

3260 Clovewood Ln
San Jose, CA 95132
Principal Investigator


This proposal described a family of techniques for providing code encryption beyond the first level of security provided by encrypting code and data in the memory and decrypting code and data in the caches inside the processor. The proposed technology, Deep Code Scrambling (DCS), was designed to work beyond and in conjunction with the first level of security, and hence providing a second level of security. In DCS, the decrypted code in the caches are virtual or scrambled codes, which need to be unscrambled in one of the processor pipeline stage before they become meaning full for the rest of the processor pipeline stages. Further more the Unscrambling key changes often and randomly, and hence providing another barrier for reverse engineering the internal algorithms of the codes.