Computer Network Operations (CNO) for Ground-based Midcourse Defense (GMD)

Period of Performance: 06/16/2006 - 06/17/2008


Phase 2 SBIR

Recipient Firm

Irvine Sensors Corp.
3001 Red Hill Avenue, B3-108 Array
Costa Mesa, CA 92626
Principal Investigator


Irvine Sensors Corporation (ISC) proposes to develop and build the Bit Processor Device (BPD) prototype hardware to demonstrate advancements in CNO initiatives by illustrating very low-latency content addressable memory searches and pattern matches. The functional performance of the BPD architecture demonstrates high-speed interconnect of memories-to-processor interface capable of supporting bandwidth I/O of 10 Gbps and higher. A novel processing algorithm using very wide words developed specifically for the BPD s memory structures from Phase I will be implemented. The low-latency architecture and algorithm allows for applications such as intrusion detection/prevention applications to be integrated with Computer Network Operations without causing performance or integration issues. The BPD architecture is built with COTS products and is open in design to integrate with agent based systems in a work-centered environment. This new capability allows for offensive measures to be executed to detect the source of such attacks and perform forensic analysis without compromising the networks bandwidth or functionality. This device can easily be integrated wherever CAMs are used or needed.