Receiver on Chip Signal Techniques and Reconfigurable Simulations (ROCSTARS)

Period of Performance: 01/03/2006 - 05/03/2008


Phase 2 SBIR

Recipient Firm

Systran Federal Corp.
4027 Colonel Glenn Highway, Suite 210
Dayton, OH 45431
Principal Investigator


The latest generation of the USAF s Monobit Receiver is being designed as a receiver-on-a-chip (ROC). The ROC will consist of an analog-to-digital converter (ADC) and a Fast Fourier Transform (FFT) unit on one silicon substrate, and simulations have demonstrated its ability to process pulsed RF signals. Systran Federal Corp. (SFC), along with its distinguished and highly-experienced team, proposes a Phase II effort to implement the novel architecture which we designed in Phase I to handle various signal modulation schemes. SFC s Phase II effort will consist of three significant research and development areas. First, we will develop and implement our signal detection architecture, which was designed specially for the Monobit Receiver system by a team consisting of the engineers responsible for the original and latest Monobit Receiver architectures and the end-user of the ROC. Second, we will use Northrop Grumman Corporation s (NGC s) brassboard Monobit demonstration platform (developed by AFRL) for verification of our architecture. The final area will be the exploration of military and commercial uses of this technology and the entire Monobit system.