Novel Concepts for Next Generation Infrared (IR) Focal Plane Arrays (FPAs)

Period of Performance: 05/17/2006 - 05/17/2008


Phase 2 SBIR

Recipient Firm

Polaris Sensor Technologies, Inc.
200 Westside Square Array
Huntsville, AL 35801
Principal Investigator


Polaris Sensor Technologies, Inc. places image preprocessing into the Read Out Integrated Circuit for next generation focal planes. The FPGAs within the ROIC/SEA present opportunities to qualify data during read out. This effort builds a flight-like algorithm testbed to determine how to divide image pre processing functions among the ROIC and the SEA. Emulators, simulation, and COTS components will create a flexible environment representing prime contractor architectures. Novel image processing algorithms are optimized to remove the cascade of functions across multiple boards and connections that add noise, add cost and increases complexity; thus impacting overall system reliability. The THAAD, Si:BIB (Blocked-Impurity-Band) and super lattice focal plane arrays utilize COTS ROICs, and this, coupled with the cascade of interfaces, compromises performance. The proposed approach is the most cost effective, lowest risk approach to improve seeker sensitivity and acquisition range. Neural networks and complementary algorithms are specifically applied to extract data of interest in low SNR MDA data. Operating in the SNR range of 2 may increase the seeker acquisition range by as much as 70%. The outcome supports new ROIC/SEA designs appropriate for flight hardware and this effort is tightly coordinated with ongoing MDA efforts.