Field Programmable Gate Array Based Channelizer

Period of Performance: 04/18/2006 - 07/17/2008

$743K

Phase 2 SBIR

Recipient Firm

Linquest Corp.
6701 Center Drive West, Suite 425
Los Angeles, CA 90292
Principal Investigator

Abstract

Our proposed radiation hardened FPGA based turbo codec development has two primary objectives critical to reducing risk on the Transformational Communication Satellite (TSAT) program. The first objective is to develop an innovative highly efficient turbo codec core solution that supports TSAT. TSAT requires significant improvement in the waveform processing capability to meet increased throughput requirements as well as dynamic changes in data rates. The turbo codec core solution is critical as it must overcome space, weight and power (SWaP) constraints that limit the number of FPGAs while overcoming the FPGA s relatively slow clock speed limitation. The second objective is the development of a prototype board with target FPGA s and associated test bed designed to meet the radiation hardening requirements in addition to the performance requirements. Both of these objectives are aimed at reducing the risk associated with FPGA/ASIC selection which has resulted in cost and schedule impacts to the AEHF program.