Schottky Barrier CMOS for Space and Missile Applications

Period of Performance: 03/31/2003 - 05/26/2004

$750K

Phase 2 SBIR

Recipient Firm

Spinnaker Semiconductor
Room 527 Shepherd Labs, 100 Union St. SE
Minneapolis, MN 55455
Principal Investigator

Research Topics

Abstract

Spinnaker Semiconductor, in partnership with Lincoln Labs in Lexington, Massachusetts, will demonstrate 25nm physical gate length NMOS and PMOS devices based on Schottky source/drain technology. Spinnaker's patent-protected Schottky Barrier (SB) CMOS technology is a fundamental and strategic leap forward for the entire high-performance silicon CMOS manufacturing industry (>$150 Billion in 2000) and is easily ported to any existing advanced silicon CMOS factory. It will enable the volume production of ultra high performance silicon ICs three to four years and one to two technology generations ahead of current industry leaders. It is broadly applicable to any high performance logic application, as well as high frequency (Ethernet, RF, wireless) applications. It is scalable with relative ease into the sub-10 nm regime and has significant performance and manufacturability advantages over conventionally architected CMOS. It is naturally and inherently radiation-hard, as it is unconditionally immune to latch-up and other effects resulting from parasitic bipolar action.