Strain-Layer Superlattice Barriers for Silicon Quantum Devices

Period of Performance: 10/17/1995 - 10/17/1997


Phase 2 SBIR

Recipient Firm

Nanodynamics, Inc.
901 Fuhrmann Blvd.
Buffalo, NY 14203
Principal Investigator

Research Topics


Phase I constructed silicon-based superlattice barriers and a barrier height of 1.7 eV has been realized. Quantum Tunneling Diodes have been designed, fabricated, and tested. Quantum processors, both bipolar and FET, will also be fabricated and tested. Linear devices, modifying from existing designs, will be constructed as well as various quantum tunneling gates will be fabricated and tested. Several academic institutions and companies will participate in the fabrications and evaluations. Anticipated Benefits: Faster, smaller processors fabrication from silicon and consistent with silicon processing technology.