Silicon Brain Architecture

Period of Performance: 07/07/1998 - 07/07/2000


Phase 2 SBIR

Recipient Firm

Irvine Sensors Corp.
3001 Red Hill Avenue, B3-108 Array
Costa Mesa, CA 92626
Principal Investigator


The technology now exists to bring human level recognition capabilities to military defense problems, at higher data rates and in environments unsustainable by humans. The proposed innovation synthesizes work at Irvine Sensors, Cal Tech, JPL, MIT, Boston University, UCSD and USC to provide a silicon emulation of the human central nervous system, including all of its sensory apparatus, to execute the sensing, discrimination, and systems control functions of ballistic missile defense. The approach emulates and exploits the massive parallelism inherent in the brain to achieve extremely high computational performance at very low power and small volume. Ultimately, petaflop performance will be attained within 20 watts and 10 cubic inches. In Phase I critical 3D interconnect feasibility was demonstrated experimentally and and investment alliance was formed to commercialize the technology. A major, unanticipated breakthrough occurred during Phase I: the invention of the #dEFT to provide massive chip-to-chip interconnect within a stack of chips. 3DEFT technology will enable truly 3D integrated circuits thus prolonging Moore's Laws. A Phase II program was planned to develop and commercialize the 3DEFT technology and apply it within the Silicon Brain Architecture consortium.