Advanced Digital Array Radar (DAR) Adaptive Beamformer and Pulse Compression Processor

Period of Performance: 08/30/2004 - 08/30/2006


Phase 2 SBIR

Recipient Firm

Systems Software International
580 Anaconda Drive
Colorado Springs, CO 80919
Principal Investigator


The proposed Reconfigurable DAR Processor (RDP) design is a large network of FPGA-based DSP nodes (augmented with a few CPU nodes) distributed over several Multi-node DSP Line Cards (MDLCs) and interconnected by a full serial mesh backplane. The Phase II effort will result in two significant products that will directly benefit several US Navy programs developing advanced RF sensors. The first product is the library of fully-debugged and well characterized DSP algorithms implemented in Xilinx FPGA firmware. Though developed specifically to support the real-time DAR functions used by the RDP, use of these validated FPGA-based algorithms would reduce schedule and cost risk for Navy programs with very-high-speed adaptive signal processing requirements. The second Phase II product is the RDP Demonstration of the DAR system design (developed under Phase I). The RDP hardware platform could be used as the processor for adaptive DAR R&D programs and as the starting point for the design of any future Navy DAR sensor. Since the hardware platform can be easily expanded to support up to 320 channels, it could also serve as the real-time processor for US Navy Electronic Warfare and Electronic Support systems requiring support for interfaces to complicated RF sensors having a large number of output channels.