Device-Quality, Low-Defect Hybrid SiC Wafers

Period of Performance: 07/23/2003 - 07/23/2005

$750K

Phase 2 SBIR

Recipient Firm

Astralux, Inc.
2500 CENTRAL AVE., # 286
Boulder, CO 80301
Principal Investigator

Abstract

Researchers at Astralux, Inc. in collaboration with PowerSicel, Inc and the University of Colorado at Boulder propose to develop hybrid SiC wafers using a novel technique. Specifically, our goal is to commercialize low-defect, epi-ready 3-inch and 4-inch SiC wafers. We will develop conducting substrates for both near-dc high voltage/power and optoelectronics, as well as semi-insulating wafers for RF power devices. Our hybrid SiC wafers are complementary to the existing bulk SiC wafers, and our value added is to reduce stress, decrease defects, increase the production volume and significantly reduce the cost of larger-area substrates. During Phase I, researchers at Astralux demonstrated 35 mm hybrid SiC wafers with an epitaxial GaN growth demonstration. All Phase I milestones were reached, the goals accomplished and we are now ready for prototype development in Phase II. In Phase II, the quality of the hybrid wafers will be validated through a SiC RF device demonstration.