Gate Oxide Screening Methodology and Surface Smoothing for Advanced SOI Space System Applications

Period of Performance: 07/12/2000 - 07/12/2002


Phase 2 SBIR

Recipient Firm

Epion Corp.
4R Alfred Circle
Bedford, MA 01730
Principal Investigator

Research Topics


Special technology and circuit architecture is under investigation for implementation of radiation hard low power electronics (LPE) which operate at low supply voltages and consume low power levels without sacrificing performance. Silicon-on-insulator (SOI) substrates have advantages which make it attractive for applications that require tolerance to radiation effects. A significant aspect regarding commercial application of SOI is the inconsistency of the gate oxide integrity (GOI). The variation in the gate oxide breakdown may be attributed to such material factors as surface roughness, defect density, or metallics. Testing is typically expensive and time consuming. An opportunity exists to establish a test methodology for smooth surfaced SOI material using a reduced mask process and ramped voltage stress testing. In the Phase I program, conventional and reduced mask MOS capacitor GOI testing indicates feasibility of the gas cluster ion beam (GCIB) process for SOI surface smoothing, achieving better GOI results. In Phase II, a variable energy GCIB process will be performed to achieve bulk-like SOI surfaces for statistically significant reduced mask GOI testing. Matching private investor funds, contingent upon Phase II award, is secured. A high probability for commercialization of the GOI test methodology and GCIB smoothing is anticipated. The nation may expect to benefit from the success of the proposed R&D for an early gate oxide screening methodology and a surface smoothing process. Commercialization of SOI substrates for space applications will be greatly enhanced by the GOI test technique and a United States manufacturing base of GCIB smoothing apparatus.