An Synchronous Testbed for Low Power DSP's

Period of Performance: 09/24/1999 - 09/30/2001

$719K

Phase 2 SBIR

Recipient Firm

Theseus Logic, Inc.
1080 Montreal Ave, Suite 200
St. Paul, MN 55116
Principal Investigator

Research Topics

Abstract

It is clear that continuing to seek performance improvement using traditional digital design and implementation techniques will not provide the "next order of magnitude" improvement in DSP performance. Theseus Logic is commercializing a unique technology that will facilitate low power, system level IC design. NULL Convention Logic - is a new and fundamentally more expressive "language" for the design of digital circuits and systems. At the system level, NCL provides: Circuits which are inherently clockless, data driven, and effectively delay insensitive, Lower power operation, Reduced EMI, Guaranteed operation over a wide range of environmental conditions, Plug and Play system integration. Under Phase I SBIR to demonstrate the benefits of NCL for low power DSP processing, Theseus is delivering an asynchronous DSP testbed. This testbed integrates a combination of existing NC CMOS ASICs and NCL programmed Xilinx FPGAs into a demonstration system. The Phase II program will evolve the design of key processing blocks for a commercial NCL DSP product designed for sub one-volt power supply operation. These blocks will be fabricated in an appropriate CMOS technology, characterized for speed/power trade-off, and delivered to the Army. BENEFITS: NCL produces circuits and systems that are clockless, data driven and effectively delay insensitive. As a result of these features, they are extremely well suited to battery operated portable systems because power consumption is inherently matched to data rate. This both conserves battery life and provides improved reliability.