Advanced Optoelectronic Pulse-Coupled Pattern Recognition Systems

Period of Performance: 11/13/1998 - 11/13/2000


Phase 2 SBIR

Recipient Firm

Bosonics, Inc.
1472 North St.
Boulder, CO 80304
Principal Investigator

Research Topics


To develop faster and larger pulse-coupled neural networks (PCNN) for image processing, Bosonics will design, simulate and demonstrate a 64 by 64 smart-detector chip. PCNNs have been shown to be effective at fast analog pre-processing of detector data, image transforms, and automatic target recognition. In Phase II, we will test the 5x5 neuron chip we designed and fabricated in Phase I. Bosonics will also 1) simulate multilayer networks and advanced optoelectronic architectures; 2) fabricate and test separate 64 by 64 processing and imager chips in CMOS; 3) flip-chip solder bump integrate the chips together; and 4) demonstrate the integrated system in an image processing system. This hardware demonstrator will be delivered along with a user manual. The chips produced under this program will lower the cost of machine vision systems by providing an integrated detector/processing function as well as increasing performance by using computationally effective PC~U'N algorithms. BENEFITS: Pulse-coupled neural networks are computationally efficient for low-level image processing. Thus, the chips developed under this program will have wide application in automatic target recognition, machine vision for automated manufacturing, and remote surveillance.