A System for Register Transfer Level (RTL) Full-Chip Area, Speed, and Power Optimization

Period of Performance: 04/17/1998 - 02/17/2000


Phase 2 SBIR

Recipient Firm

Tera Systems, Inc.
2105 S. Bascom Ave.
Campbell, CA 95008
Principal Investigator

Research Topics


The "design gap" is a growing disparity between what semiconductor manufacturers can build with today's deep-submicron (DSM) processes and what integrated circuit (IC) designers can create using top-down electronic design automation tools. Tera Systems, Inc. is bridging the design gap by; developing a register-transfer-level (RTL) design and analysis system that will enable IC designers to automate structured-custom design.The current-generation of top-down IC design tools were developed to solve issues of design complexity and functional verification without giving adequate consideration to physical implementation details. With DSM processes, wire-parasitic delays rather than gate delays dominate, causing top-down design tools to create sub-optimal designs. Engineers must use manual techniques at the expense of productivity to get high performance silicon.Our proposed system includes a new class of RTL analysis and optimization tools that will enhance existing top-down IC design systems by implementing a performance-driven design paradigm. Our methodology will enable users to enter, analyze, debug, optimize, and implement their designs by working exclusively with RTL models. Full-chip design, analysis, and optimization will run orders-of-magnitude faster than conventional gate-level tools, thereby enabling truly interactive design.