Design of GPS Receiver Module on a Single Silicon Chip

Period of Performance: 06/11/1998 - 09/15/2000

$750K

Phase 2 SBIR

Recipient Firm

Physical Research, Inc.
25500 Hawthorne Blvd., Suite, 2300
Torrance, CA 90505
Principal Investigator

Abstract

Our Phase I study has proven the feasibility of a single-chip GPS RF receiver. This Phase II submittal proposes to finalize the circuit design, layout, fabrication and demonstrate the performance of a single chip GPS RF receiver front end with digital functions. We are proposing to integrate all external functions and components such as filters and the oscillator tank circuitry onto a single substrate, reducing the size, power dissipation and cost. Because this chip would be CMOS, adding a digital demodulator will be trivial. In addition, we will add programmability to the GPS receiver that will allow it to demodulate all aspects of the GPS signals in both RF bands. We can achieve these goals through an innovative architecture and state-of-the-art RF circuit design. This level of integration has not yet been achieved because the necessary circuits and techniques have only been pioneered and demonstrated in the past few years by our design team. Final tests of out RF chip will also be performed by a major GPS system manufacturer using their existing GPS DSP.