Modeling of CMP and Photolithographic Pattern Printing Equipment Variations and the Impact on Circuit Performance

Period of Performance: 04/01/1998 - 07/01/2000


Phase 2 SBIR

Recipient Firm

PDF Solutions
333 West San Carlos St, Ste. 625
San Jose, CA 95110
Principal Investigator


To ensure the profitability of US semiconductor manufacturers, and a reliable supply of integrated circuits (ICs) to the US military, this SBIR identifies and attacks software and modeling issues presented by two major sources of design-dependent process variation: chemical mechanical polishing (CMP) and photolithographic pattern printing. A cogent study of dependent process variation is of great importance because such variation highlights a need for greater communication between the IC manufacturing and design communities, two groups traditionally insulated from each other. The proposed project has three general thrusts: 1) to develop software tools for measuring the impact of spatial and structural process variation on circuit performance, including detailed net analysis via solid modeling and detailed statistical cell performance characterization; 2) to investigate advanced, full-chip process models for chemical mechanical polishing (CMP) and photolithographic pattern printing, including multi-layer effects and correlations between those two processes; and 3) to build a pareto of the impact of spatial process variation on the performance of integrated circuits over time. Taken as a whole these efforts enable design for manufacturability (DFM) through simulation and modeling as well as chart a course for future research into spatial process variation.