VHDL Behavioral Simulation Acceleration Engine

Period of Performance: 07/25/1993 - 07/25/1995


Phase 2 SBIR

Recipient Firm

MTL Systems, Inc.
3481 Dayton-Xenia Rd.
Dayton, OH 45432
Principal Investigator

Research Topics


The objective of the Phase II program is to produce a design specification for the Accelerator for VHDL Simulation (AVS), and to quality the design through performance modeling and prototype testing. The preliminary design and initial performance models from the Phase I work will form the basis of this design effort. Tasks in the Phase II effort include Design Completion, Performance Modeling, Prototype Development and Testing, and Design Specification Production. The design, which was pre-qualified through Phase I performance modeling, is based upon an innovative, 5-processor accelerator node architecture, with a 2-dimensional-mesh node interconnection structure. It also employes virtual time and innovative memory management methods. It was shown, through the Phase I performance modeling, to be capable of significant acceleration, in a user-tranparent paradigm. In addition to the qualified design specification, the prototypes will be delivered, to provide a laboratory-grade accelerator for immediate application or continuing research.