Development of a Digital Optical Interconnection Technology

Period of Performance: 08/19/1991 - 02/19/1992


Phase 2 SBIR

Recipient Firm

Technical Imaging Services, Inc.
PO Box 1237; 380 Farmingdale Road
Jackson, NJ 08527
Principal Investigator


The Phase I SBIR effort resulted in the gate-level design of a Gaussian elimination processor that solves systems of linear equations and resulted in the finding that design restrictions such as (1) uniform logic operations, (2) simple regular interconnects, and (3) small fan-ins and fan-outs do not by themselves pose severe limitations on digital optical procesor performance, but taken in conjunction these restrictions do in fact reduce overall performance, primarily in increased latency and increased gate count. The Phase II effort proposes the development of novel optical interconnection technology that relaxes the fan-in/fan-out and regular interconnection constraints. The development of this interconnect technology is coordinated with the design and fabrication of mask sets for an all optical digital procesor that is being designed and built in the Photonics Center at Rome Laboratory/Griffiss AFB. The Phase I Gaussian elimination architecture will be modified to correspond with the interconnection technology that results from this Phase II effort. The anticipated results from the Phase II effort are a viable optical interconnection technology for a digital optical processor, and a physical design for an optical Gaussian elimination processor that utilizes this interconnection technology.