Athena Sensor Arithmetic Processor (ASAP)

Period of Performance: 10/10/1993 - 10/09/1995

$163K

Phase 2 SBIR

Recipient Firm

THE Athena Group, Inc.
GAINESVILLE, FL 32601
Principal Investigator

Research Topics

Abstract

The proposed Phase II ASAP project will research, develop, and prototype a new class of digital signal and image processor we refer to as the Athena Sensor Arithmetic Processor or ASAP. ASAP is based on Athena's patent-pending logarithmic residue number system (LRNS) processor technology, which has a significant advantage over other fixed-point arithmetic systems in terms of speed and area. Because an LRNS processor is small, many can be placed on a single chip, resulting in a technology we call an "array on a chip." The developed LRNS technology will be used to research new baseline signal processors as well as a 231x231 DFT which can operate at a sustained real-time rate of 100 frames per second. The resulting design will be tested using simulation and prototyped on a PC board. Low-cost continuation options are offered to allow expanded system capabilities, if desired by the sponsor.