Radiation Hard CMOS Sensors for Detector at High Energy Colliders

Period of Performance: 06/12/2017 - 03/11/2018

$150K

Phase 1 SBIR

Recipient Firm

Sensor Creations, Inc.
5251 Verdugo Way Suite I
Camarillo, CA 93012
Firm POC
Principal Investigator

Abstract

Sensor Creations, Inc. (SCI) has developed a monolithic, deep depletion CMOS image sensor (CIS) technology based on a 0.18 m mixed signal CMOS process by ON-Semiconductor using 8’’ wafers. For fabrication, we are using very high resistivity (6.5 kΩ x cm) Si wafers. In a post process, SCI thins the finished CMOS wafers to a thickness between 50-400 m, depending on the targeted application, and adds a backside electrode to form a vertical PIN photodiode. SCI has also developed the technology to package even the thinnest silicon sensors without the need for wafer bonding or a chip carrier to provide mechanical support. This makes our fully depleted high rho CMOS technology particularly suited for tracking applications in High Energy Physics (HEP) experiments. When a voltage is applied across this vertical PIN diode, the high resistivity Si sensor becomes fully depleted. This has been demonstrated to provide faster charge collection and better charge confinement to only a few pixels. In addition, radiation hardness up to neutron equivalent fluence levels of 2*1016/cm2 is expected. This high radiation tolerance is a result of the high resistivity N-type silicon which will undergo type inversion as it accumulates radiation damage yet remain fully functional. One of the unique characteristics of our technology is the possibility to monolithically integrate complimentary circuitry into the pixel array. This is fundamentally different from all consumer type CIS processes where the pixel circuitry can only be built with one type of transistor, typically NMOS. For the proposed sensor, we will leverage that capability and develop a fully digital radiation detector with low power, high speed logic circuitry inside the pixel array. The sensor design is derived from the orthopix architecture which is used for Monolithic Active Pixel Sensors (MAPS) with very high frame rate requirements, low occupancy and high reconstruction efficiency. But to support the comparatively high occupancy of 0.1 %, corresponding to 1049 hits per megapixel resolution, we must improve the baseline orthopix idea. In the improved design, the pixel array is divided into sub-blocks for which projections are calculated inside the array. Despite the higher number of projections that must be calculated, the power dissipation for the sensor array is minimal because the tracking information is already digitized inside the pixel array. To realize such a complex CMOS IC design on high resistivity N-type material, SCI has to develop a process design kit (PDK) and logic libraries for industry standard EDA tools. Key aspects of that design kit are: LVS (Layout versus Schematic) and DRC (Design Rule Check) verification rule files for the quadruple well structure; Electrical design rule (EDR check to certify the complete design for latch up and antenna violation. Because standard CMOS processes are based on p-type material, and do not employ as deep implants with corresponding wider design rules, a standard PDK and logic library cannot be used for designing in our high rho technology. This PDK will be made available to external U.S. design centers at the end of phase II to extend the CMOS process offerings in the United States, thereby maximizing the nationwide commercial benefits of this research project. Our estimates indicate that the targeted cost of $100,000 per m2 can be achieved, if the individual sensors are kept reasonably small, i.e. no stitching should be applied. Based on SCI’s experience in the design of very large focal plane arrays for astronomy applications, the achievable yield for large stitched ICs is incompatible with the targeted budgets for next generation HEP detectors.