12-bit 32 Channel 500MSps Low Latency ADC

Period of Performance: 02/21/2017 - 11/20/2017


Phase 1 SBIR

Recipient Firm

Pacific Microchip Corporation
3916 Sepulveda Boulevard #108 Array
Culver City, CA 90230
Firm POC
Principal Investigator


Particle accelerators need precise, real-time control of the particle beams used to create the conditions required for Nuclear Physics (NP) experiments. These control systems require digital low latency feedback through a high linearity and dynamic range ADC. Densely packed electronic circuits employing high performance multichannel digitizers result in excessive heat dissipation. Thus, ADCs become the bottleneck devices in NP instruments. Pacific Microchip Corp. proposes to develop a 12-bit 32 channel 500MSps low power, low latency ADC ASIC. The ADC will employ a novel two-step conversion based on a merged sample & hold circuit, a residue C-DAC and a shared 6-bit flash core ADC. The proposed ASIC will include an array of 32 ADCs operated in parallel, will support channel-to-channel and ASIC-to-ASIC synchronization and will feature the JESD204B output interface. In order to extend the ADC’s applicability to other instruments and systems within NP and HEP facilities, the ADC will feature increased radiation hardness. In Phase I, the ADC’s architecture will be developed and modeled, the critical circuits will be designed and the proof of feasibility based on simulations will be provided. Phase II will result in the fabricated and tested ADC ASIC’s prototype ready for commercialization in Phase III. Commercial applications and other benefits. Due to the increasing role of digital signal processing in state of the art electronic systems, an ADC becomes a generic building block employed to perform direct digitization and multichannel signal processing for a great number of applications including sensor systems, control loops and RF receivers. Thus, the multichannel low power, high sampling rate 12-bit ADC will be demanded for a large number of tasks. Radiation hardness will expand the proposed ADC ASIC’s applicability to other DOE and NASA science programs and to the systems under development by the industry. To ensure the highest outcome of the developed technology, we plan to license the ASIC as an IP block ready to other interested parties for integration with other blocks (both analog and digital) for a system-on-a-chip (SoC) solution. According to the latest market study released by Technavio, the global data converter market is expected to reach $4.24 billion by 2020, growing at a CAGR of almost 6%. This projection confirms the great potential for the proposed ADC.