SBIR Phase I: An Automated Design Flow to Build Energy Efficient Vision Processing and Machine Learning Chips for the Internet of Things

Period of Performance: 06/01/2017 - 01/31/2018


Phase 1 SBIR

Recipient Firm

Reduced Energy Microsystems, Inc
264 Dore St Array
San Francisco, CA 94103
Firm POC, Principal Investigator


The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project will be to bring data-driven decision making to new areas of human interaction with technology. The Internet of Things (IoT) embodies the hardware, software, and systems that enable monitoring and managing objects in the physical world electronically. IoT devices will enable performance optimization of systems and processes, time savings for people and businesses, and quality of life improvements. The total economic impact of the IoT is estimated to exceed $11 trillion by 2025. However, reaching these lofty estimates requires advances in hardware technology, particularly for energy-constrained IoT devices that must gather data, make decisions based on the data gathered, and communicate to a larger system under a limited power budget. The company will develop low power embedded computer vision systems and machine learning algorithms for use in for virtual/augmented reality, drones, surveillance cameras and other applications. The proposed project advances the commercialization of new ?timing-resilient? chip technology, which promises unparalleled power efficiency by bringing dynamic voltage scaling to IoT devices with minimal impact on traditional design flows. Changing the operating voltage of a device can lead to significant energy efficiency improvements, yet many circuit designers do not take advantage of this technique due to increased design time and complexity. This proposal focuses on the development of a comprehensive computer-aided design (CAD) flow that transforms existing synchronous designs into more efficient asynchronous timing-resilient designs that support a wide range of voltages. The proposed project addresses three aspects of the automated flow: design for manufacturability and test; analysis of logic cell libraries at lower voltages; and interfacing the new timing-resilient circuits with synchronous circuits. The flow combines simulation, analysis, synthesis, place-and-route, and test with similar efficiency as standard commercial flows. This research aims to limit the additional testing overhead of the converted design and the performance impact of interfacing with traditional circuits to within 10% of synchronous counterparts. The development of this new flow will enable chip designs that are fundamentally more energy efficient and help bring the full power of machine learning to smaller form factors.