Reconfigurable Memory or Central Processing Unit (CPU) Instruction Architecture

Period of Performance: 09/12/2016 - 09/11/2018


Phase 2 SBIR

Recipient Firm

Bluerisc, Inc.
28 Dana St
Amherst, MA 01002
Firm POC
Principal Investigator


The proposed solution automatically co-creates a per-device-unique, configurable secure processor, as well as associated enabling software build environment, enabling unique execution environments, instruction set, and protected memory interfaces. The unique execution environments and protected memory interfaces provide foundational resilience against software, black box, physical, as well as side-channel attacks based on power analysis and fault injection.