Implementation of the Code-free Dual-frequency GPS Receiver Design

Period of Performance: 01/01/1989 - 12/31/1989

$500K

Phase 2 SBIR

Recipient Firm

S M Systems & Research Corp.
8401 Corporate Dr - Ste 510
Landover, MD 20785
Principal Investigator

Abstract

A RECEIVER DESIGN HAS BEEN DEVELOPED DURING PHASE I FOR CODE-FREE DUAL-FREQUENCY (CFDF) GPS RECEIVER TO MEASURE 1) THE DIFFERENTIAL CARRIER PHASE, 2) DIFFERENTIAL GROUP DELAY AND 3) AMPLITUDES ON THE L(1) AND L(2) GPS FREQUENCIES. THIS DESIGN DOES NOT REQUIRE ACCESS TO THE P-CODE AND ENABLES THE DETERMINATION OF THE DIFFERENTIAL GROUP DELAY HENCE THE ABSOLUTE VALUE OF THE TOTAL ELECTRON CONTENT (TEC). DURING PHASE II THE RECEIVER DESIGN WILL BE HARDWARE IMPLEMENTED AND TRADE-OFFS IN ANTENNA GAIN, PROCESSING GAIN AND INTEGRATION TIME WILL BE OPTIMIZED. A PROTOTYPE RECEIVER WILL BE BUILT AND TESTED TO DEMONSTRATE THE REALIZATION OF THE DESIGN OBJECTIVES. NECESSARY TESTS AND CALIBRATION WILL BE MADE ON THE RECEIVER AND IT WILL BE USED WITH THE ANTENNA DESIGN CHOSEN TO RECEIVE GPS SIGNALS AND THE RECEIVER PERFORMANCE WILL BE DEMONSTRATED TO ACHIEVE THE DESIGN GOALS. TWO ADDITIONAL RECEIVERS WILL BE FABRICATED SO THAT THE THREE RECEIVERS ARE DEPLOYED IN ACTUAL GEOGRAPHICAL ENVIRONMENTS, NAMELY, IN EQUATORIAL, MIDDLE AND HIGH LATITUDES. THE FIELD TEST DATA WOULD BE EVALUATED TO DETERMINE THE RECEIVER PERFORMANCE. BASED ON THIS EXPERIENCE, ADJUSTMENT WILL BE MADE ON THE RECEIVERS TO REALIZE THE ORIGINAL DESIGN OBJECTIVES.