Monolithically Integrated Rad-Hard SiC Gate Driver for 1200 V DMOSFETs

Period of Performance: 06/10/2016 - 12/09/2016


Phase 1 SBIR

Recipient Firm

Genesic Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
Firm POC, Principal Investigator


This two-phase SBIR program targets the need for highly integrated SiC-based electronics systems by developing analog and digital circuits that can be fully integrated with 4H-SiC power switching devices, enabling eventual realization of a monolithic, highly integrated gate driver circuit. Specifically, the final goal of this program is to develop and demonstrate a fully integrated, isolated, high-side/low-side gate driver architecture, having an integrated SiC power MOSFET. In addition to integrated resistors and capacitors, development of SiC CMOS technology will entail the demonstration of lateral SiC NMOSFETs and the more challenging SiC PMOSFET devices with adequate performance and radiation hardness. During Phase I, the development of a rad-hard SiC PMOS process will be investigated. In parallel, capitalizing on GeneSiC�s already developed SiC NMOS process, an NMOS-only gate drive buffer circuit will be designed and implemented on the same host substrate as 1200 V SiC DMOSFETs. Compact device models will be generated during Phase II from the results of the SiC NMOS/PMOS process development. Pending successful development of a rad-hard SiC PMOS process during Phase I, Phase II will focus on building an entire SiC CMOS-based gate drive circuit and integrating it with a 1200 V SiC DMOSFET.